1. Field of Invention
The present invention relates to semiconductor devices with improved switching accuracy and operational speeds at reduced power consumption levels. More particularly, the present invention relates to MOS semiconductor devices and circuits having control electrodes that improve the switching accuracy and speed of the devices and circuits while reducing the power consumption thereof, and while permitting fabrication using standard MOS fabrication techniques and equipment.
2. Description of the Related Art
In recent years, large scale integration technology has steadily improved so that more complex integrated circuits can be fabricated. However, limitations in current VLSI technology preclude reliable use of such technology in high speed circuit applications. Attempts to overcome these limitations have involved the controlling of the switching threshold voltage and resulted in the use of functional semiconductor devices such as neuron MOS (vMOS) transistors and circuits (e.g., EEPROMs) fabricated using conventional silicon process technology. The vMOS transistor is a MOS transistor having a feature wherein a single vMOS element has capabilities similar to that of a neuron. FIG. 24 illustrates a vMOS transistor structure. The vMOS transistor includes a source electrode region 55 and a drain electrode region 56 formed by doping an impurity into a semiconductor substrate 57 to a high-concentration level. A gate insulating film 50, a floating gate 48, and a gate insulating film 51 are formed successively on the semiconductor substrate 57, and a plurality of signal input gates 45 and 46 are formed on the gate insulating film 51. The floating gate 48 is surrounded by the gate insulating films 50 and 51, and the signal input gates 45 and 46 are capacitively coupled with the floating gate 48. The gate voltage of the floating gate 48 is given as a weighted linear addition of the signal voltages applied to the signal input gates 45 and 46. The signal input gate 45 is capacitively coupled with the floating gate 48 via a capacitor C.sub.1 created across the gate insulating film 51, and the signal input gate 46 is capacitively coupled with the floating gate 48 via a capacitor C.sub.2 created across gate insulating film 51. If the voltages applied to the signal input gates 45 and 46 are represented by V.sub.g1 and V.sub.g2, respectively, the voltage (.phi..sub.F) on the floating gate 48 can be written as .phi..sub.F =(C.sub.1 V.sub.g1 +C.sub.2 V.sub.g2)/(C.sub.1 +C.sub.2). If the floating gate voltage .phi..sub.F is lower than a threshold voltage V.sub.th, the transistor is in an off-state, and if the floating gate voltage .phi..sub.F is greater than the threshold voltage V.sub.th, the transistor is in an on-state. In FIG. 28, V.sub.sub, V.sub.S, V.sub.d denote a substrate voltage, source voltage, and drain voltage, respectively.
FIG. 25 represents a circuit diagram of a 2-input vMOS transistor having a structure similar to that shown in FIG. 24, and FIG. 26 illustrates a graph of drain current vs. gate voltage for the 2-input vMOS transistor shown in FIG. 25. For simplicity, it is assumed here that the capacitance of both C.sub.1 and C.sub.2 are 1 (unity). In this case, when (V.sub.g1 +V.sub.g2)/2&gt; V.sub.th, a current flows through the channel of the 2-input vMOS transistor. Therefore, if V.sub.g1 and V.sub.g2 are regarded as an input voltage and a control voltage, respectively, then the threshold voltage of the transistor seen by V.sub.g1 is controlled by V.sub.g2. Although, the overall gate voltage required for the channel to be turned on is constant, the apparent threshold voltage seen at a signal input gate is changed by the voltage applied to the other signal input gate. Thus, the vMOS structure shown in FIG. 24 can function as a variable threshold device. Discussions of current vMOS transistor technology can be found in "Nikkei Micro Devices" pp. 101-109 (January 1992) and in a paper published in "Technical Report", The Institute of Electronics, Information, and Communications Engineers, ICD93-6, by Shibata and Omi, pp.39-46.
The vMOS transistor structure can be used to construct semiconductor circuits having CMOS characteristics. FIGS. 27a and 27b illustrate a functional layout of a semiconductor inverter having input gates 61, a floating gate 62 and gate oxide films 63 and 64 that is fabricated using vMOS transistors and has CMOS operating characteristics. FIG. 28 illustrates a circuit diagram of the CMOS-type inverter seen in FIGS. 27a and 27b.
The vMOS transistor structure can be used to construct an EEPROM semiconductor circuit. As seen in FIG. 29, the EEPROM includes a source electrode region 58 and a drain electrode region 59 that are formed in a semiconductor substrate 60 by diffusing an impurity to a high-concentration level. A gate insulating film 52, a floating gate 49, and a gate insulating film 53 are successively formed on the semiconductor substrate 60, and a control gate 47 is formed on the gate insulating film 53. The floating gate 49 is surrounded by the gate insulating films 52 and 53, and the control gate 47 is capacitively coupled with the floating gate. The gate insulating film 52 has a portion 54 with a very thin thickness. Under a certain bias condition, the thin portion 54 acts as a tunnel oxide film so that a tunnel current flows between the drain electrode region 59 and the floating gate 49 through the thin portion 54 acting as a tunnel oxide film. FIG. 30 illustrates a circuit diagram of the EEPROM shown in FIG. 29. The floating gate 49 can be at either one of two different voltage levels depending on whether a charge is injected, through the tunneling effect, from the drain 59 into the floating gate 49 through the tunnel oxide film 54. The difference in the floating gate voltage results in a difference in the threshold voltage seen by the control gate 47. As a result, the voltage required for the control gate 47 to turn on the device so that a sufficiently large current flows through a surface region of the semiconductor substrate 60 between the source 58 and the drain 59, can have either one of two different values.
Although the above described vMOS transistor is fabricated with substantially the same structure as conventional MOS devices in terms of the source electrode regions, the drain electrode regions, and the silicon substrates, the vMOS transistor differs from conventional MOS transistors in that their threshold voltages can be varied. The vMOS transistor can be used in the fabrication of various semiconductor circuits including memory circuits that have advantages over conventional MOS circuits. For example, such semiconductor circuits are fabricated from vMOS transistors having similar operating characteristics as CMOS circuits, and such semiconductor circuits can be fabricated using a substantially smaller number of vMOS transistors as compared to conventional MOS circuits.
However, one limitation of such vMOS based semiconductor circuits is that the threshold voltages of the vMOS transistors are determined by the capacitance between the floating gate and a plurality of input gates. As a result, the threshold voltage of each transistor is influenced by the dimensions (e.g., the area) of the gate electrode. However, inherent variations in the fabrication processes used to produce such vMOS based semiconductor circuits makes it difficult to adequately control the dimensions of the gate electrode. These inherent variations reduce the switching speed and accuracy of circuits fabricated from vMOS transistors. That is, the operational characteristics of such vMOS based circuits are directly determined by the accuracy of the microstructure fabrication process or microlithography technology. The inherent variations in the fabrication process are magnified with, for example, VLSI circuits where as the complexity of the circuit increases the number of vMOS transistors used also increases.
One reason for the inherent variations is in the fabrication of vMOS transistors. When fabricating vMOS transistors it is necessary to eliminate capacitive coupling between an overlapping portion located between the input and floating gates and the channel region of the vMOS transistor. To eliminate the capacitive coupling a two-dimensional expansion of the vMOS transistor structure is made. As a result, the size of the transistor is increased and the circuits are not suitable for high density integration.
The advancements made in VLSI technology have spurred the evolution of many digital techniques and systems capable of processing analog input signals. The increase in the implementation of digital systems has increased the need for highly accurate analog-to-digital converters that operate at high speeds and that can be fabricated using existing equipment and processes. For example, the performance of digital video equipment and measuring instruments is often limited by the performance of the A/D converter employed. Flash A/D converters were developed for use in high-speed A/D conversion applications.
FIG. 31 illustrates a circuit configuration for a conventional n-bit flash A/D converter. In this conventional n-bit flash A/D converter, an input signal voltage V.sub.in is applied in common to a series of 2.sup.n -1 comparators 84, and 2.sup.n -1 reference voltages generated by a series of resistors 83 are supplied to the corresponding comparators. Comparators having a reference voltage greater than the input signal voltage V.sub.in all provide an output of logic 0 while comparators having a reference voltage smaller than the input signal voltage V.sub.in all provide an output of logic 1. The boundary between logic 0 and logic 1 of the outputs of these comparators, typically called a thermometer code since the outputs are similar to the indication of a thermometer, is detected by a differentiating circuit 85. The n-bit outputs are converted by an encoder 86 to an n-bit binary digital signal and output via output terminals D.sub.n, D.sub.n-1, D.sub.n-2, . . . , D.sub.2, D.sub.1.
The comparators used in conventional flash A/D converters are typically constructed with bipolar transistors. FIG. 32 illustrates a schematic diagram of an example of such a comparator constructed with bipolar technology. Flash A/D converters constructed with bipolar comparators require a greater number of bipolar transistors resulting in significant variations in the operating characteristics between the transistors. A discussion of comparators constructed with bipolar technology can be found in "Linear Circuit Data Book", Japan Texas Instruments Inc., pgs. 8-53, (1989). Due to limitations in fabricating bipolar transistors, it is difficult to reduce the variations in the operating characteristics between the comparators in conventional flash A/D converters. Such variations in the operating characteristics among comparators reduce the switching accuracy and speed of bipolar flash A/D converters. To illustrate, the output code of a comparator array (the thermometer code) ideally consists of a consecutive series of "1s" at lower positions and a consecutive series of "0's" at upper positions, wherein the transition between logic 1 and logic 0 occurs only once at the boundary between the series of "1's" and the series of "0's". In reality, however, when operating at high frequencies the thermometer code can include a plurality of transition points due to jitter arising from the variations in performance among comparators. When a thermometer code having such an error is converted by the encoder to a binary code, the resultant binary code includes coding errors (sometimes called A/D converter glitch). For the above reason as well as others, conventional bipolar A/D converters tend to generate significant errors when operating at high frequencies.
Various attempts have been made to solve the above problem by improving the circuit configuration of the flash A/D converter. FIG. 33 illustrates a multi-step flash A/D converter that uses sample-and-hold circuits so that an analog voltage provided as an input signal is sampled and held by the sample-and-hold circuits and converted in parallel into upper and lower bits. A discussion of the multi-step flash A/D converter can be found in "Analog Techniques For VLSI", by Kusunoki, Iwata and Akasawa p.184 (1989). Another known technique is to add latches to the respective comparators in the above-described multi-step flash A/D converter so that data is temporarily stored in the latches making it possible for each stage of the converter to operate in a pipe-line fashion. This technique is known as a cascade A/D converter.
However, one limitation of these flash A/D converters is that they require complex circuits which are difficult to implement and fabricate on a large scale.
Furthermore, since these flash A/D converters are based on the non-saturation analog circuit technology constructed with bipolar transistors, they have greater power requirements than saturation-type digital circuits such as CMOS based circuits. As a result, heat dissipation becomes a significant problem with such bipolar based converters, and thus the operating characteristics of the A/D converter may vary with changes in the operating temperature.
In the publication entitled "High-Speed A/D Converters: Recent Technology and Future Trends" by Matsuzawa, ICD91-84, pp.21-28 an example of a flash A/D converter using MOS transistors instead of bipolar transistors is discussed. The A/D converter discussed by Matsuzawa is a 2-stage parallel CMOS A/D converter constructed with chopper type comparators composed of MOS transistors. FIG. 34 illustrates such a converter where inverters 87 are of conventional CMOS type.
In the flash A/D converters constructed with bipolar transistors, and the 2-stage parallel A/D converters constructed with CMOS technology discussed above, the circuit complexity, power requirements, heat dissipation factors, and switching accuracy and speed requirements makes it difficult and/or inefficient to fabricate such circuits using large scale integration technology.